1. Field of the Invention
The present invention generally relates to a disk apparatus, and in particular to a disk apparatus having a data reproducing system for reproducing information continuously recorded on a disk or recorded along a data recording guide groove having a periodically wobbling sector format formed on an optical disk, which the data reproduction apparatus rapidly adjusts a frequency of a reproduced tracking error signal in a frequency control system for rough adjustment, and subsequently, continuously generates clock signals locked to the reproduction signal in a phase control system for fine adjustment, even in a stage before a CLV control of a spindle motor is established.
2. Description of the Prior Art
Recently, there has been increasing utilization of various disks such as DVD-RAM disk having a sector format formed with a recording guide groove periodically wobbling. When information is read out of such a disk, the read-out data signal is supplied to a PLL circuit which generates a clock synchronized with the read-out signal to reproduce digital data synchronized with the clock signal.
The following explains a schematic structure of a sector format formed on a disk with reference to FIG. 17. In this sector format example, a guide track formed in a RAM portion on the disk includes a groove portion and a land portion. The guide track is formed in such a manner that a laser beam spot projected from an optical pick-up head tracks a specified position when information is recorded on the disk. The groove portions (depicted by real lines) and the land portions (depicted by dotted lines) are continuously alternated every one rotation of the disk where the information can be recorded both on the groove and land portions. The guide track is divided into a plurality of sectors and each of the sectors is comprised of an ID region and information recording region. In this example, although the guide track is formed of a spiral format, it may be of a concentric circle format, and also it may be reversible in spiral direction.
FIG. 15 shows an example of a conventional data reproducing apparatus using an analog PLL (Phase Locked Loop). In this construction, 101 denotes an optical disk, 102 denotes an optical pick-up device which applies laser beams to the optical disk and generates an electrical signal in accordance with the strength or quantity of the reflected light therefrom, 103 denotes a preamplifier for amplifying the read-out signal output of the optical pick-up device, 104 denotes a waveform equalizer for adjusting the frequency characteristics of the output signal of the preamplifier 103 and equalizing the waveform to be suited for binarizing, and 105 denotes a binarizing circuit for binarizing the output signal of the waveform equalizer 104, which the circuit blocks 104 and 105 constitute a waveform rectifier.
Reference numeral 110 denotes a PLL which is comprised of a phase comparator 106, loop filter 107 and a voltage control oscillator (referred to as "VCO" hereinafter) 108 for generating a PLL clock for synchronization. The phase comparator 106 compares the output signal of the binarizing circuit 105 with the output clock signal of the VCO 108 to thereby generate a phase error or difference in phase, and the loop filter 107 removes unnecessary frequency band i.e., high frequency components among from the output signal of the phase comparator 106, and VCO 108 generates a PLL clock having a frequency proportional to the output voltage of the loop filter 107. Reference numeral 109 denotes a latch circuit which latches the output reproduction signal of the binarizing circuit 105 and generates the reproduction readout data in synchronization with the PLL clock outputted from the VCO 108.
The following explains the operation of the above conventional example of the analog PLL type. The readout information signal of the optical disk 101 by way of the optical pick-up device 2 is amplified by the preamplifier 103 and adjusted in frequency by the waveform equalizer 104 and the resultant signal is supplied to the binarizing circuit 105. In the binarizing circuit 105, the reproduction signal output of the waveform equalizer 104 is binarized, i.e., converted into "0" or "1" by a slice level process, and the binarized reproduction signal is supplied to the latch circuit 109 and also supplied to the PLL 110. The binarized reproduction signal has a waveform of two values 0 and 1 alternated at intervals each having a period integer times a given bit period T. Accordingly, the PLL 110 obtains a bit period T from the period of each value 0 or 1 and generates a clock signal having a period in accordance with the bit period T.
In the PLL 110, the binarized signal and the PLL clock outputted from the VCO 108 are compared in phase by the phase comparator 106 to perform a feedback control so as to make the phase error output equal zero. At this process, the VCO 108 adjusts its oscillation frequency by way of a voltage control so as to cancel the phase error, and generates a PLL clock having a frequency proportional to the output voltage of the loop filter 107, which the PLL clock is synchronized with the binarized signal. The synchronized clock signal is fed back to the phase comparator 106 and also supplied to the latch circuit 109. Then, the binarized reproduction signal supplied from the binarizing circuit 105 to the latch circuit 109 is generated as the digital reproduction data in synchronization with the PLL clock signal supplied from the VCO 108, so that the synchronized digital reproduction data is supplied to the later reproducing circuitry system.
In the conventional analog PLL type apparatus, however, there have been problems such that, the apparatus is easily influenced by undesirable environmental or aging changes and differences in parts, that high integration thereof can not be made, and that the apparatus can not cope with the case when taking account of incorporation of a circuit which requires synchronized multi-valued readout data.
Meanwhile, a conventional digital PLL has been developed using a variable frequency oscillator (referred to as "VFO" hereinafter) instead of a VCO, where an oscillation frequency is adjusted in accordance with the phase difference and is divided by a frequency divider, and the resultant obtained clock signal is fed back to the phase comparator. However, in this conventional digital PLL processing method, when a disk player having a high data processing speed is used, the frequency of the clock is high, and therefore it is difficult to attain a VFO for oscillating further several times higher frequency, and even when such a VFO is realized, the apparatus should be of high cost.
Therefore, another type of digital PLL is considered, incorporating a frequency comparator in combination with a phase comparator as shown in FIG. 16. In this construction shown in FIG. 16, an optical pick-up device 122 applies laser beams to an optical disk 121 and receives the reflection beams thereof from the optical disk. Thus the readout information signal is supplied to a preamplifier 123 as an electric reproduction signal in accordance with the quantity of the received reflection beams. The readout signal after amplified by the preamplifier 123 is supplied to an A/D converter 124 in which the readout signal is sampled in synchronization with the clock signal which is generated by the VCO 131 and then converted to a digital signal having a digital value of a given bit number (i.e., digitized). The digitized readout signal is rectified in waveform by a transversal filter 125 to be suitable for binarization. Thus, the resultant digital readout signal is supplied to the phase comparator 126 and also supplied to the digital reproducing system in the later stage.
Meanwhile, the frequency comparator 127 is supplied with both a reference clock REFCLK having a frequency corresponding to a central frequency of the reproduction signal and an output clock signal of the VCO 131 and calculates the frequency difference (error) therebetween. The calculated frequency error is supplied to a selector 128. When the frequency error is decreased to a given level or lower, the frequency comparator 127 transmits a switching signal to a timing control circuit 132.
On the other hand, the the phase comparator 126 detects the zero-cross point which is a turning point of the digital readout signal at which the value thereof is changed from positive (plus) to negative (minus) or changed from negative (minus) to positive (plus), and calculates the phase difference between two sampling values before and after the zero-cross point. Thus the calculated phase difference is supplied to the selector 128. The timing control circuit 132 receives the switching signal from the frequency comparator 127 and changes over the connecting terminals from a terminal Sb side to a terminal Sa side when the frequency difference is lower than a predetermined level. By this switching connection by the selector 128, a D/A converter 129 selectively receives the frequency difference data or the phase difference data and converts the selected difference data into an analog form. The analog signal is then supplied to a loop filter 130 to remove undesirable high frequency components contained therein, and the resultant analog signal is supplied to the VCO 131 which generates a PLL clock signal by reducing the error data to zero.
However, in this digital PLL type apparatus, in the case where the optical pick-up device is largely moved in a radial direction of the disk when a seeking or the like operation is caused, lock of the PLL is difficult in the stage before the CLV control of the spindle motor is established, which results in taking a long seeking time.
Moreover, when reproduction signal has different center frequency, the frequency control should be conducted with change of the reference clock. In this case, another frequency synthesizer is required to be incorporated, which results in high cost of the apparatus.
Also, in this construction, only one D/A converter is provided, and the D/A converter has a limited bit number. Therefore, in order to obtain a resolution accuracy higher than a constant level, the adjustment controllable range of the operation frequency is limited, and therefore, a sufficient resolution can not be obtained when a large range of operation frequency is to be covered in a range e.g., from one time to 32 times speed in reproduction.